Multiprocessor computer architectures typically arc realized by connecting planar arrays of separate processor boards together through a backplane bus. The processors are board-mounted microchips located along with other chips at computing nodes. Several nodes are located on each board. The node arrays may be under the control of a "host" computer. Alternatively, the nodes may be synchronized by the input data itself.
Node interconnection configurations must be varied to suit a particular application, for example, to form a systolic or linear array for efficiently solving particular problems.
Spatial efficiency is critically necessary in multiprocessor computers. Although some spatially efficient multiprocessor computing: structures are disclosed in the prior art, it is desirable to pack still more computing capacity into smaller volumes.
One possible structure for achieving smaller volumes is a stacked processor board array, wherein the processors are rectangular 4-ported chips with the ports typically denoted north, east, west, and south. These board modules are termed "Multi-chip Modules", or "MCMs". The boards can be stacked and electrically connected as described in U.S. Pat. No. 5,049,982 assigned to applicants' assignee.
The electrical pathing disclosed in the cited patent application of Lee et al. 1-6 does not afford sufficiently flexible routing options, however. Realizing a large number of possible computing architectures inexpensively in a standardized stacked modular regime requires that the processors of the standard hardware elements be interconnectable with as much variability as possible.
One factor which makes routing flexibility difficult to achieve is that the routing of signals to and from the processors of the stacked array is more complex than routing in two dimensions. Routing path crossover problems are an example. Present approaches to avoiding crossover problems, which occur in routing between and among processor elements of stacked boards, tend to create paths that am circuitous, heat-generating, and space-inefficient.
Accordingly, one object of the invention is to maximize the number and variety of possible computing architectures that can be realized in a stacked-board multiprocessor.
Another object of the invention is to increase the computing density (computing power per unit physical volume) of a multiprocessor computer.
A further object of the invention is to provide a multiprocessor computer of high density, which is also scalable to meet a wide range of computing applications.